1. Field of the Disclosure
The present disclosure generally relates to semiconductor devices including three-dimensional (3D) field effect transistors (FETs).
2. Background Art
With the advance in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, and high speed communication systems. To meet these demands, the semiconductor industry continues to scale down dimension of FETs, and also increase packing density of FETs on an integrated circuit (IC) to accommodate a larger number of FETs on an IC. However, this approach of scaling down and closely packing of FETs on ICs has limitations. The scaling down of devices to smaller dimensions can introduce short channel effects. In addition, closely spaced FETs may suffer from disturbances such as electron leakage, noise coupling, or electrostatic coupling. These limitations can degrade the operating characteristics and performance of the FETs over time.
To overcome such limitations, transition from planar FET to non-planar, e.g., 3D FET architecture has been considered. Relative to planar FETs, 3D FETs offer improved channel control and therefore, reduced short channel effects. These non-planar FETs are 3D structures having vertical structures (also referred as “fins”) as the transistor body and they are generally referred as 3D FETs or FinFETs. While a channel region in a planar FET is within the substrate with a gate structure placed above the channel region, the channel region of a 3D FET is placed above the substrate with a gate structure wrapped around the channel region, providing better gate control of the 3D FET current. There are two current 3D FET process flows: one based on silicon-on-insulator (SOI) substrates, and another based on bulk silicon substrates.
The present disclosure will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digits) in the reference number.